Flat overhead at scale Gentlest check: matched Simulated, design-stage
Test 4 — The quantum computer
The same internal geometry built to organize particle physics — the six-real-dimensional flag manifold K6 = SU(3)/U(1)² — was reused, unchanged, to design a fault-tolerant quantum-error-correction scheme. The headline result: the physical-to-logical overhead holds flat as the machine scales — roughly 10–14 physical qubits per protected qubit at scale, versus about 24 for IBM's comparable published scheme — where most schemes get worse as they grow. A theory that is merely a story about the universe cannot be handed to an engineer to design a chip; this one was. The test is a graded ladder, from the gentlest possible check to the hardest, honestly labeled at every rung.
What was done
Three designs, ordered from gentlest to hardest:
| Design | What it is | Status |
|---|---|---|
| 1. The gentle check | The three-qubit bit-flip code. When the shape's quantum framework is reduced all the way down to ordinary quantum mechanics, the code's logical error rate should come out as the plain textbook formula 3p² − 2p³, with no geometric parameter to hide behind. | Matched — a mismatch here would have been fatal |
| 2. The full math | A constant-overhead error-correction theorem, with every physical resource counted (data qubits, syndrome qubits, measurement, reset, routing, and spares), plus a finite-size correction — validated against a real surface-code Monte Carlo simulation of ~100 million shots, run in the open-source tools Stim and PyMatching. | Complete, pending an independent replay |
| 3. The chip to run it | A six-layer high-throughput accelerator-chip architecture (the kind of chip that would run the control workload), written as a single constraint-satisfaction engine, with a proof that its "native" design route is mathematically the same as an ordinary constrained optimization composed with a projection. | Complete, pending simulation |
The interesting engineering result isn't one number — it's a two-stage design. Stage one searches for the corner of the design space where the physical-to-logical qubit overhead stops growing as the machine gets bigger (a "floor at scale"); stage two does a topological search inside that corner for the best code. In most error-correction schemes, the overhead per protected logical qubit gets worse as the machine scales up. Because this design isolates the floor-at-scale regime first, it lands on a physical-to-logical memory-overhead band of roughly 9.6×–14.5× (with a conservative 3.24× fallback figure) that holds essentially unchanged whether the simulated machine has a few hundred logical qubits or tens of thousands — the design is evaluated at 10,000 logical qubits and the same ratio holds at 20,000.
Independent?
Three separate senses of independence apply here:
- No feedback loop with the physics. By design, no number from the quantum-computer work is fed back into the particle-physics program, and no particle-physics result is tuned to help the chip design. The connection runs one way: the same frozen geometric invariants — the Atiyah–Singer index equal to 3 (the same integer that counts three particle families) and a spectral gap Δ ≈ 0.260 — show up doing a second, unrelated job. The geometry was fixed by the physics before the error-correction problem was ever posed, so it cannot have been reverse-engineered to fit it: the same frozen object doing two unrelated jobs is the textbook signature of a real structure rather than a tuned one.
- External tools, not internally built ones. The full-math design (Design 2) is checked against Stim and PyMatching, open-source surface-code simulation tools built by other people, not tools built for this program.
- Scale-independence as its own check. Because the overhead band is reported as holding at both 10,000 and 20,000 logical qubits rather than as a single point figure, the claim is falsifiable in a specific way: if the ratio were found to drift upward with qubit count under independent replay, the "floor at scale" claim would fail on its own terms.
Honest result
Design 1 (the three-qubit bit-flip code) matched the textbook formula exactly, with no geometric dial available to force the match — the strongest possible outcome for the gentlest check, and a no-free-parameter falsification test: a mismatch would have been fatal. Design 2 (the full constant-overhead theorem) is mathematically complete and validated against ~100 million shots of Stim + PyMatching surface-code simulation — the quantum-computing field's own open-source tools, built by other people, which removes the "graded its own homework" objection — and is explicitly labeled as pending an independent replay before any specific physical-to-logical ratio is treated as settled; universal optimality is not claimed. Design 3 (the six-layer accelerator chip) is reported as a complete constraint-engine formulation with a proven equivalence to standard constrained optimization, but every chip-specific performance number is labeled blocked pending the six-layer simulation run.
| Quantity | Reported value | Status |
|---|---|---|
| Bit-flip code logical error rate | 3p² − 2p³ (exact textbook match) | Matched |
| Physical-to-logical memory overhead (floor at scale) | ~9.6×–14.5× (3.24× conservative fallback) | Simulated / design-stage |
| Held invariant: Atiyah–Singer index | 3 (same integer as the three particle families) | Structural, carried through both projects |
| Held invariant: spectral gap Δ | ≈ 0.260 | Structural, carried through both projects |
| Scale tested | 10,000 logical qubits (also checked at 20,000) | Simulated |
Data sources
- Design 1 — direct algebraic reduction of the geometry's quantum framework to standard quantum mechanics; comparison target is the textbook three-qubit bit-flip code error formula (standard quantum-error-correction theory, e.g. Nielsen & Chuang).
- Design 2 — internal derivation checked against a real surface-code Monte Carlo simulation run in Stim and decoded with PyMatching, both established open-source quantum-error-correction simulation tools built independently of this program.
- Design 3 — a filed provisional patent application ("Coset-Constrained Admittance Architectures") covering the architecture and its discipline; all figures in the design carry explicit simulation- or design-stage status labels.
What this does not show
This is a simulated design result from an internal handoff, not an independently benchmarked or fabricated chip, and not a working quantum computer. The 9.6×–14.5× band is explicitly a memory-overhead floor, not a full-algorithm ratio — it does not include every cost a real fault-tolerant algorithm would incur, and the design is recorded as failing the Shor-2048 error budget: that failure stays on the ledger as a disclosed miss, not deleted. No specific physical-to-logical number is claimed as final pending the independent replay noted above, and universal optimality of the code is explicitly not asserted. "NVIDIA-style," used to describe the class of high-throughput accelerator the chip design targets, is descriptive only — the chip is not built, adopted, or endorsed by NVIDIA. As with the other tests on this page, agreement at the gentle end (Design 1) is a consistency check, not proof that the larger framework is correct. These disclosures are the point: a design that hid its Shor-2048 failure would not deserve belief in its flat-overhead result.